1. Field of the Invention
The present invention relates to clock generators and, in particular, to an emitter-coupled logic (ECL) gate configuration that allows variations in the bias current for controlling propagation delay. The disclosed ECL gate configuration has particular application in a voltage controlled ring oscillator.
2. Discussion of the Prior Art
A voltage controlled oscillator (VCO) generates periodic signals which are converted into a square wave output which can be used to provide timing pulses in various logic circuits. The output frequency of a VCO is a function of its input control voltage.
VCOs are commonly used in phase-locked loop (PLL) circuits. As shown in the FIG. 1 block diagram, a general purpose PLL 10 typically includes a phase comparator 12, a low-pass filter 14 with some gain, and a VCO 16. The phase comparator 12 compares the frequency and the phase of the input signal and of the VCO 16 and generates either a positive or a negative error voltage V.sub.e which is filtered and applied, as V.sub.d, to the VCO 16. If the input signal is within the capture range of the PLL 10, then the VCO 16 will lock onto the input frequency f.sub.s and generate an output signal of the same frequency as f.sub.s with a small fixed phase difference. Once the VCO 16 is locked onto the input signal, its output frequency f.sub.o will vary over the locking range as the input frequency f.sub.s varies.
VCOs have been implemented in the past using transistor-transistor logic (TTL) technology in a ring oscillator configuration. Conventional TTL logic gate circuitry utilized for this purpose is shown in FIG. 2. It includes three series-connected, TTL gates comprising Schottky-clamped NPN transistors T1, T2 and T3, respectively, together with corresponding load resistors R1, R2 and R3. As shown in FIG. 2, the output of this TTL gate configuration can be controlled by adjusting the supply voltage V.sub.CC applied to the load resistors R1, R2 and R3.
TTL technology represents a compromise between speed and power. The speed-power product of this technology is approximately linear. That is, increased speed results in increased power dissipation, and vice versa, up to a point at which the maximum speed limitation of the gate is reached.
Furthermore, as is well known, when a transistor saturates, a certain amount of time is required before it comes out of saturation. Thus, in digital logic gates, saturation is a speed limitation factor. TTL circuits use transistors in the saturating mode. Therefore, as stated above, while they experience relatively low power dissipation, TTL circuits do not possess the speed characteristics required in some applications.
Emitter-coupled logic (ECL) technology does not allow transistors to saturate. Therefore, ECL gate speeds can be maximized.
FIG. 3 shows a conventional, non-saturating ECL gate configuration. It includes two differential NPN input transistors E1 and E2 with corresponding load resistors R1 and R2 connected between the collectors of the respective devices E1 and E2 and the supply voltage V.sub.CC. Two diodes D1 and D2, together with resistor RB, bias the base of NPN current source transistor E3 to a two diode level, thus providing a one diode voltage drop across current source resistor R3. This ensures that the voltage swing of resistors R1 and R2 is also one diode since the emitter current and collector current of devices E1 and E2 will be equal, input devices E1 and E2 being configured as an emitter-coupled pair.
The logic swing of the ECL gate shown in FIG. 3 is controlled by the fact that the two load resistors R1 and R2 and the current source resistor R3 are matched. The propagation delay of the gate is determined by the power level set by the load resistors R1 and R2.
Thus, the ECL gate shown in FIG. 3 is basically a differential amplifier with load resistors R1 and R2 that are kept small enough in value to allow corresponding input transistors E1 and E2 to remain out of saturation, even when the differential amplifier is fully switched so that only one of the input transistors E1 or E2 is "on."
However, the fixed values of the load resistors R1 and R2 prevent the control required in VCO applications, since the input control voltage applied at the collectors of devices E1 and E2 remains constant.
Therefore, it would be highly desirable to have available a technique for providing variability in the resistive load of ECL input devices, while ensuring that if the resistive load of one input device changes, all input device resistive loads are changed to be consistent.